The input/output terminals of a semiconductor integrated circuit need a protection element (hereinafter, referred to as an ESD (Electrostatic Discharge) protection element) that protects an internal circuit from an ESD applied from a terminal electrode (hereinafter, referred to as a PAD).
FIG. 5 illustrates an example conventional ESD protection element of a semiconductor integrated circuit. The structure illustrated in FIG. 5 causes a source 1, a bulk 2, and a drain 3 of a MOS transistor to actuate as a bipolar transistor, thereby utilizing the MOS transistor for an internal circuit as an ESD protection element. The portion indicated by a reference numeral 4 in the figure is the gate of the MOS transistor.
When the MOS transistor utilized as a circuit element is used as the ESD protection element, it becomes unnecessary to form an element exclusive for an ESD protection, and thus the manufacturing process of the semiconductor integrated circuit can be shortened.
Moreover, in a case in which the drain is directly coupled with a PAD as the MOS transistor at an output stage, when the MOS transistor itself has an ESD withstandable characteristic, such a MOS transistor serves as a protection element, and thus it becomes unnecessary to additionally dispose an ESD protection element. Accordingly, the use of the MOS transistor also as the ESD protection element is desirable from the standpoint of the use efficiency of a chip area. In particular, it becomes a remarkable advantage in the case of a high-voltage MOS transistor that is often utilized as a MOS transistor at an output stage.
Conversely, microfabrication and higher withstand voltage are required for MOS transistors from the standpoint of a circuit operation. The ESD withstandable characteristic of recent MOS transistor subjected to microfabrication and made so as to be withstandable against a high voltage remarkably decreases, and such a MOS transistor is unable to serve as an ESD protection element. This tendency is quite apparent in the case of, in particular, high-voltage MOS transistors with a large heat generation amount. Accordingly, in the case of semiconductor integrated circuits that need a drain breakdown voltage that is equal to or higher than 15 V, it becomes a mainstream to additionally form an element exclusive for an ESD protection.
One of the reasons why it is difficult to cause a MOS transistor with a high drain breakdown voltage to serve as both circuit element and ESD protection element is a hot-carrier deterioration of an NMOS transistor. In the case of an NMOS transistor with a high withstand voltage, in order to ensure a drain breakdown voltage and a lifetime of hot-carriers, it is necessary to provide a drift region 6 of a low concentration in a drain region 3 so as to ease a drain electric field. FIG. 6 is a diagram illustrating a relationship between the drift region 6 and the drain region 3. The portion indicated by a reference numeral 5 in the figure is a high-concentration region which has higher concentration than that at the drift region 6.
In the low-concentration drift region 6, when the MOS transistor turns into a bipolar operation, a Kirk effect (base push-out effect) is likely to occur, and when an ESD occurs, a thermal destruction due to the concentration of electric fields is likely to occur at a boundary portion with the high-concentration region 5. In order to suppress the Kirk effect, it is necessary to form the impurity concentration of the whole drift region 6 as high as possible, and at the same time, as illustrated in FIG. 7, to form a middle-concentration region 7 with a middle impurity concentration between the impurity concentration of the drift region 6 and the impurity concentration of the high-concentration region 5 in the drain region 3, so as to make the concentration gradient in the drain region 3 to be gentle.
However, making the concentration of the drift region 6 to be higher results in the reduction of a hot-carrier lifetime, and the hot-carrier lifetime and the ESD withstandable characteristic are in a trade-off relationship. This trade-off relationship becomes remarkable when a gate insulating film is thin. Even in the case of a MOS transistor which requires a high drain breakdown voltage, it sometimes does not require such a high voltage for a gate electrode. In this case, it is required to form a gate insulating film thin to reduce the on resistance of the MOS transistor (e.g., SiO2: 12 nm or so). When the gate insulating film is formed thin, it is necessary to dope impurities for a threshold control in a channel region at a relatively high concentration so as to control the threshold of the MOS transistor.
When, however, the impurity concentration of the channel region is set to be high, since the channel region and the drain region have opposite impurity conductivities, as illustrated in FIG. 8, the concentration gradient of the impurities becomes extremely large at a boundary portion (PN junction) where a channel region 8 having a high impurity concentration and the drain region 6 adjoin with each other. When the impurity concentration gradient becomes sharp, the acceleration of electrons is promoted, the occurrence of impact ions becomes noticeable, and thus a hot-carrier deterioration becomes remarkable. Hence, in the case of NMOS transistors with a high withstand voltage of a drain, when, in particular, a gate insulating film is thin, it becomes further difficult to accomplish both ESD withstandable characteristic and hot-carrier lifetime.
As explained above, in order to allow an NMOS transistor with a drain breakdown voltage that is equal to or higher than 15 V to serve as both circuit element and ESD protection element, it is necessary to form a drain structure that suppresses a characteristic deterioration by hot-carriers at minimum to form a drift region with a concentration as high as possible.
Patent Document 1 discloses, as a technology of reducing a hot-carrier deterioration, a MOS transistor with a BLDD structure (a structure having a further low-concentration diffusion layer under a diffusion layer). According to the technology disclosed in Patent Document 1, when the MOS transistor operates, a drain current is caused to flow in a bypassed manner from a substrate surface to move the location where hot-carriers are produced apart from the substrate surface, thereby to prevent the produced hot-carriers from charging in a gate insulating film and a side wall.
Moreover, another technology of reducing a hot-carrier deterioration is to set the impurity concentration of a channel region below a gate electrode to be lower at a drain side than a source side. This eases an electric field in a PN junction forming a drain region, thereby suppressing an impact ionization. This technology is disclosed in, for example, Patent Document 2.